Correction, October 3, 2026: Earlier versions of this page said TSMC CoWoS was "sold out" and stated lead-time ranges as fact. TSMC has not said "sold out" on its 2026 earnings calls, and it does not publish lead times or CoWoS capacity. This version quotes what TSMC did say and labels lead times, bookings and capacity figures as reported estimates.
Semiconductor allocation in 2026 is a three-dimensional constraint problem: securing wafer starts is no longer enough — teams must simultaneously lock advanced-packaging slots and HBM supply. And of the three, advanced packaging is the binding one. This tracker maps where capacity is and isn't across foundry nodes and packaging technologies, with the live, queryable version in our Allocation Dashboard and API. For the argument on why lead time — not raw capacity — is the real ceiling, see Why CoWoS Lead Times Are the Real AI Bottleneck.
CoWoS: The Binding Constraint
The most acute bottleneck in AI hardware is advanced packaging, not wafer starts. As of late 2025, both of TSMC's 2.5D packaging families — CoWoS-S (silicon interposer) and CoWoS-L (RDL + local silicon bridges, used for Blackwell and Rubin) — were reported fully booked, with lead times of roughly 52–78 weeks. TSMC itself has put it differently: on its July 16, 2026 earnings call, CEO C.C. Wei said the company's "packaging capacity is so tight that now it's limiting my customers' growth." That describes rationing. We found no "sold out" statement in TSMC's 2026 earnings calls, and the lead-time ranges come from trade reports, not from TSMC.
Total CoWoS demand has roughly tripled in two years: an estimated ~370,000 wafers in 2024, ~670,000 in 2025, and approaching ~1.0 million in 2026. Estimates put TSMC's monthly capacity ramping from about 75–80k toward 120–130k WPM by the end of 2026 (TSMC does not disclose CoWoS capacity) — and the lines are reported to stay booked anyway. That is the defining feature of this cycle: capacity is growing fast, yet the booking window has not loosened.
Source: Morgan Stanley via 36Kr / Astute; TrendForce, 2025–2026 (estimates)
Concentration is the other defining feature. NVIDIA is estimated to hold roughly 60% of CoWoS capacity — about 595,000 wafers — and has reportedly booked more than half of TSMC's 2026–2027 CoWoS expansion. Together, the top three customers (NVIDIA, Broadcom, AMD) account for an estimated 85%+ of capacity. A caution on granularity: the aggregate concentration figure is widely cited, but individual non-NVIDIA wafer counts (e.g. specific Broadcom or AMD numbers) are contested across sources and should be treated as unreliable. NVIDIA's packaging draw is driven by B200 Blackwell and its Rubin successor.
Samsung's I-Cube and X-Cube lines and TSMC's OSAT partners (Amkor) offer some overflow capacity, but at lower throughput and with their own 26–39 week lead times — not enough to relieve the core constraint.
Advanced Logic: 2nm and 3nm Tight
One tier upstream, leading-edge logic is also constrained, though less acutely than packaging. Secondary reports describe TSMC's 2nm/A16 (N2) capacity as booked well into 2028, with lead times in the 78–156 week range; we could not trace either figure to TSMC. A small number of lead mobile and HPC customers are reported to hold the bulk of initial N2 allocation. Wafer pricing for 2nm is expected to exceed $30,000, a step up from the ~$20,000 range at N3.
N3 sits one tier down, with reported lead times around 52–78 weeks as NVIDIA, leading mobile SoC vendors, and HPC customers absorb output. TSMC said in July 2026 that it is adding three more 3nm fabs, in Taiwan, Arizona and Japan, to support a "robust multi-year pipeline of demand." N7 and mature nodes, by contrast, are widely available at 4–17 weeks — the constraint is concentrated almost entirely at the leading edge and in packaging. Model how node choice flows through to die cost in the Chip Price Calculator.
HBM: The Memory Multiplier
The third constraint dimension is HBM. HBM3E (both 8-hi and 12-hi) is allocated for 2026, with prices up double digits year-over-year. HBM4 is ramping into late 2026; SK Hynix took 50% of HBM revenue in Q2 2026, Samsung 33% and Micron 18% (Counterpoint Research), and SK Hynix reportedly supplies roughly two-thirds of NVIDIA's HBM4. Track live HBM dynamics in HBM Market Analysis and the HBM Qualification Tracker.
Correction, October 6, 2026: This article put SK Hynix's HBM share at ~62% with no period or source and said Micron was gaining on Samsung. The 62% was Counterpoint Research's Q2 2025 share of HBM shipments. On revenue, Counterpoint puts SK Hynix at 50%, Samsung at 33% and Micron at 18% in Q2 2026.
The compound effect matters: a current-generation AI accelerator needs front-end wafers and a CoWoS slot and HBM allocation. With CoWoS rationed and HBM allocated, no single supply-chain intervention resolves the bottleneck — which is why allocation has become a board-level planning problem.
| Constraint | 2026 status | Reported lead time | Note |
|---|---|---|---|
| CoWoS-S / CoWoS-L | Allocated — TSMC: capacity limits customers' growth | 52–78 weeks (reported) | Reported fully booked; demand shifting to CoWoS-L |
| N2 / A16 (2nm) | Tight — reported booked into 2028 (unconfirmed) | 78–156 weeks (reported) | Lead customers reported to hold bulk of initial allocation |
| N3 | Tight | 52–78 weeks (reported) | NVIDIA / mobile SoC / HPC; TSMC adding three N3 fabs |
| N7 + mature | Available | 4–17 weeks (reported) | Little constraint |
| HBM3E (8-/12-hi) | Allocated (2026) | — | Prices up double digits YoY |
| HBM4 | Ramping | — | SK Hynix 50% of HBM revenue (Q2 2026); ~2/3 of NVIDIA HBM4 |
A Note on Provenance
Allocation numbers deserve more skepticism than they usually get. Most 2026–2027 figures in circulation are forward projections that trace back to a single sell-side estimate (Morgan Stanley), reproduced second-hand across trade press and social channels. That doesn't make them wrong — but it means the apparent "consensus" is often one source echoed many times.
This is why our Allocation Dashboard tags every datapoint with its source, date, and a confidence tier, and exposes the same data through a machine-readable API (/api/v1/allocation) and the get_foundry_allocation MCP tool. Aggregate figures (total demand, NVIDIA's rough share, the >85%-locked headline) are higher-confidence; individual per-customer wafer counts are flagged low-confidence or contested. The value isn't a single number — it's tracking how these estimates move over time.
What This Means for 2027 Planning
- Secure CoWoS in parallel with wafer slots. The backend is the binding constraint; a front-end slot without a packaging slot doesn't ship. Compare packaging options in the Packaging Model.
- 2nm requires being in the queue already. With N2 reportedly booked into 2028, new entrants should target N3E or plan for A16 volume later.
- Lock HBM before committing front-end starts. HBM3E is allocated; memory supply is a gating decision, not a detail.
- Watch the booking window, not just capacity. Added WPM does not immediately shorten lead times when capacity is pre-booked — see the lead-time bottleneck analysis.