Correction, October 3, 2026: Earlier versions of this article stated as fact that CoWoS capacity was "fully booked" with 52–78-week queues and that ~85% of it was pre-booked, and put TSMC's CoWoS capacity at 75–80k wafers per month "through 2024" (that estimate is for end-2025). TSMC publishes neither CoWoS capacity nor lead times, and has not said "sold out" on its 2026 earnings calls. This version labels those figures as estimates and adds what TSMC has said and filed.
The question of how much semiconductor capacity has been added for AI accelerators, GPUs, HBM, and processors — and what that means for wafer starts per month at TSMC, Samsung, and Intel — is one of the most practically important questions in the industry right now. This analysis answers it directly, with the economic and operational context that procurement teams and strategic planners actually need.
The 2024 Capacity Expansion: What Actually Happened
Entering 2024, the AI hardware supply chain was operating under conditions it had never seen before: demand for GPU and accelerator silicon was growing faster than any previous compute cycle, HBM was in structural shortage, and advanced packaging had emerged as a constraint that wafer-fab investment alone could not resolve.
TSMC's response was the most aggressive expansion in its history. Having already invested approximately $240B in capacity over the prior decade across nine sites with dozens of 300mm fabs, TSMC accelerated further [5]. The company's advanced-node fabs in Taiwan — running N4/N5 processes for NVIDIA, AMD, and others — were operating at high utilization throughout 2024, with lead times on AI-related allocations extending well beyond typical planning horizons.
Samsung Foundry pursued a parallel ramp, particularly on its SF5 node, positioning its ~$13k-per-wafer pricing as a cost alternative to TSMC's ~$19k N5/N4. The economic gap is real — roughly 1.5x on wafer cost alone — but yield-adjusted cost-per-good-die on leading-edge AI logic has historically narrowed that advantage, and NVIDIA's primary volume remained at TSMC throughout this period.
Intel, meanwhile, was executing a foundry strategy pivot under its IDM 2.0 framework. Its near-term contribution to AI accelerator manufacturing was limited: Intel 16nm runs at approximately $5k per wafer, suited for legacy and embedded workloads rather than flagship AI silicon. Intel's more meaningful play — advanced packaging via EMIB and Foveros, and the 18A process node ramp — is a 2025–2027 story rather than a 2024 capacity story.
Wafer Starts Per Month: The Numbers and What They Mean
Wafer starts per month (WPM) is the canonical measure of fab throughput. For CoWoS-capable capacity — the advanced packaging process required for HBM-integrated AI accelerators — TSMC's trajectory through 2024 and into 2026 is the critical data series.
Estimates from industry sources put TSMC's CoWoS capacity at approximately 75–80k WPM at the end of 2025, with a target of 120–130k WPM by end-2026 [1]. TSMC does not disclose CoWoS capacity, so treat both figures as estimates. Even so, that is a roughly 1.6x increase in a single year — a substantial ramp by any historical standard.
The problem is the demand curve has outrun it. An estimated 85%+ of TSMC's 2026–2027 CoWoS capacity is reportedly already locked through long-term supply agreements, with NVIDIA alone having secured more than half of the expansion [1]. This creates a structural pre-booking dynamic: new capacity is absorbed before it comes online, meaning headline WPM growth does not translate proportionally into available spot capacity for new customers or programs.
The firmest public evidence of that pre-booking is in TSMC's own filings. TSMC reports "temporary receipts from customers," which it defines as "payments made by customers to the Company to retain the Company's capacity"; the part due beyond twelve months rose from NT$43.3B at the end of 2025 to NT$92.4B at June 30, 2026 [7]. The figure covers all of TSMC, not CoWoS alone.
For TSMC's Arizona GigaFab specifically, each individual fab is sized at 15–20k WPM at initial ramp, scaling toward 30–40k WPM at maturity [2][4]. TSMC has committed to up to 12 fabs at the Arizona site with a total investment of ~$165B — the largest foreign direct investment in U.S. history [4]. The first fab is already producing advanced chips; the second fab completed construction with equipment installation targeted for Q3 2026 [4]. At mature state, the Arizona complex could represent 10–20% of TSMC's total U.S.-accessible advanced-node capacity [2], but that is a 2028–2030 outcome, not a 2024 one.
Wafer Economics Comparison by Node and Foundry
| Node | Foundry | Est. Wafer Cost (300mm) | Primary AI Workload |
|---|---|---|---|
| N5/N4 | TSMC | ~$19k ($16k–$21k) | NVIDIA H100/H200, AMD MI300X |
| SF5 | Samsung | ~$13k ($11k–$15k) | Alternative AI logic (yield-dependent) |
| N3/N3E | TSMC | ~$20k ($17k–$22k) | Next-gen AI logic transition |
| SF3 | Samsung | ~$15k ($13k–$17k) | Competing N3-class workloads |
| N7 | TSMC | ~$10k ($8k–$11k) | Mature AI inference, networking |
| Intel 16nm | Intel | ~$5k ($4k–$5k) | Legacy compute, embedded |
| TSMC 28nm | TSMC | ~$3k | Mature node, analog, mixed-signal |
HBM: The Memory Bottleneck That Wafer Starts Cannot Fix
No discussion of 2024 AI capacity expansion is complete without HBM. High-bandwidth memory is not manufactured at a logic foundry — it is produced at DRAM fabs by SK Hynix, Samsung Memory, and Micron — but its allocation dynamics are as constrained as anything in the logic supply chain.
Looking at the manufacturing cost structure of current-generation AI accelerators makes the stakes clear:
AI Accelerator Manufacturing Cost Breakdown (Selected SKUs)
| Chip | Logic Die + Test/Assembly (est.) | HBM Cost (est.) | Packaging Cost (est.) | Total Mfg Cost (est.) |
|---|---|---|---|---|
| NVIDIA H100 SXM5 | ~$1,220 | ~$1,350 | ~$750 | ~$3,320 |
| NVIDIA H200 SXM5 | ~$2,000 | ~$2,175 | ~$750 | ~$5,150 |
| NVIDIA B200 | ~$2,400 | ~$2,900 | ~$1,100 | ~$6,400 |
| NVIDIA GB200 Superchip | ~$5,500 | ~$5,800 | ~$2,200 | ~$14,200 |
| AMD MI300X | ~$1,200 | ~$2,900 | ~$1,200 | ~$5,300 |
Note: "Logic die + test/assembly" combines the logic die with test and assembly costs. For the H100 SXM5, we model that ~$1,220 as roughly $300 for the logic die and ~$920 for test and assembly against the ~$3,320 total (the total tracks Raymond James estimates; the component split is Silicon Analysts modeling). All figures are estimates based on public cost modeling. See Chip Cost Calculator for scenario modeling.
For the H100 SXM5, HBM represents approximately 41% of total manufacturing cost. For the GB200 Superchip, HBM and packaging together account for roughly 59% of total build cost. As generations advance from H100 to Blackwell — with HBM stacks growing and memory per unit jumping from 80GB to 192GB or more — the HBM cost share grows, not shrinks.
SK Hynix held the leading position in HBM3 and HBM3e qualification for NVIDIA's platforms through 2024, with Samsung and Micron in various stages of qualification for successive generations. The qualification race, which we track separately in The HBM Qualification Race, directly determines which memory suppliers can participate in the most valuable AI accelerator programs.
Advanced Packaging: The Binding Constraint
If wafer starts and HBM allocation represent the two primary supply variables, CoWoS advanced packaging is the variable that integrates them — and the one that became the hardest limit on AI hardware availability by mid-2026.
CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's interposer-based packaging technology that enables the tight silicon-to-HBM integration required by flagship AI accelerators. At a full-package cost of roughly $600–$900 for H100-class designs (point estimate ~$750, rising with substrate complexity and HBM stack count; CoWoS-L variants for B200-class parts run closer to ~$1,100, per Bernstein/TrendForce analyst estimates), it is a smaller line item than the HBM bill but exceeds the cost of the logic die itself — and it is the longest-lead and least-substitutable.
As we detailed in Why CoWoS Lead Times — Not Wafer Capacity — Are the Real AI Bottleneck, sell-side estimates put 2026 CoWoS demand at ~1M wafers, largely committed in advance, with NVIDIA holding approximately 60% [1]. This means a customer who secures wafer-level allocation but not packaging allocation cannot ship product — making packaging the true gating item.
Trade reports put CoWoS booking-to-delivery lead times at roughly 52 weeks at their late-2023 peak, well above balanced-market norms through 2024 as demand growth outpaced TSMC's packaging facility expansion, and describe allocation queues for new capacity orders of roughly 52–78 weeks in 2026. TSMC publishes neither figure. What it has said, on its July 16, 2026 earnings call, is that its "packaging capacity is so tight that now it's limiting my customers' growth" [8]. TSMC's Arizona GigaFab plans include four advanced packaging facilities [4], which would meaningfully increase CoWoS-equivalent capacity — but again on a multi-year timeline.
Strategic Implications for Procurement and Planning
For teams managing AI hardware supply chains, the 2024 capacity expansion picture translates into several actionable realities:
First, headline wafer-start capacity numbers from any foundry are necessary but not sufficient information. The constraint stack — wafer allocation, HBM allocation, packaging allocation — must all be evaluated simultaneously. A position in one does not guarantee a position in the others.
Second, TSMC's pricing power is structurally reinforced by this dynamic. With an estimated ~85% of advanced AI packaging capacity pre-booked, customers paying up front to retain TSMC capacity, and Samsung still closing a yield gap on leading-edge AI logic, TSMC can and does price accordingly. The ~$19k N5/N4 wafer price versus Samsung's ~$13k SF5 reflects both process premium and effective monopoly pricing on packaging-integrated AI volume.
Third, the geographic diversification of advanced capacity — TSMC Arizona, potential Samsung expansion in Taylor, Texas, and Intel's Ohio and Oregon investments — is a multi-year project. 2024 and 2025 supply is overwhelmingly Taiwan-originated, with meaningful U.S.-based advanced-node capacity arriving in volume no earlier than 2026–2027 for TSMC Arizona and later for others.
For deeper cost modeling on specific AI accelerators, the Chip Cost Calculator and HBM Market Analysis tools allow scenario-level analysis of how node, HBM generation, and packaging architecture interact on total manufacturing cost.
References & Sources
[1] Silicon Analysts internal research synthesis — AI Data Center Value Chain Analysis; CoWoS Lead Times analysis; Foundry Allocation Status Q1 2026.
[2] Social media / investor thread analysis of TSMC Arizona fab capacity parameters, citing 15–20k WPM initial ramp and 30–40k WPM mature targets per fab.
[4] "TSMC's $165B Arizona GigaFab: Reshaping US Chips [2026]." Industry analysis of TSMC Arizona expansion scope, fab count, packaging facility count, and construction status.
[5] Fab site and process technology analysis: TSMC multi-fab advanced-node roadmap and historical capex trajectory (~$240B over 10 years); TSMC nine-site, multi-300mm-fab operational footprint.
[7] TSMC, Form 6-K with Q2 2026 consolidated financial statements (SEC, August 2026) — note on temporary receipts from customers.
[8] TSMC Q2 2026 earnings conference call, July 16, 2026 (transcript via Investing.com).